As depicted in FIG. 1, a typical phase-locked loop (PLL) 100 includes a phase frequency detector (PFD) 110, a charge pump (CP) 120, a loop filter (LF) 130, and a voltage-controlled oscillator (VCO) 140. The PFD 110 detects the phase difference between a reference clock and a feedback clock generated by the VCO. Usually, two logic signals, denoted in FIG. 1 as UP signal and DN signal, are used by the PFD 110 to represent the phase difference between the two clocks. Each time a phase comparison is made, an UP pulse, a DN pulse, or both, may be generated. If the reference clock is leading the feedback clock (e.g., the rising edge of the reference clock occurs before the rising edge of the feedback clock), an UP pulse is generated, and either no DN pulse is generated or a DN pulse shorter than the UP pulse is generated. If the feedback clock is leading the reference clock, a DN pulse is generated, and either no UP pulse is generated or an UP pulse shorter than the DN pulse is generated. The difference in the width between the UP pulse and the DN pulse is indicative of the phase difference between the two clocks.
The CP 120 receives the two logic signals UP and DN and converts them into a current signal. For example, the CP 120 generates a positive (e.g., out-going) current pulse in response to a UP pulse, and generates a negative (e.g., in-coming) current pulse in response to a DN pulse. The output of the CP 120 is connected to the LF 130, which typically includes a resistor in series with a capacitor to convert the output current from the CP 120 into an output voltage. The output voltage from the LF 130 is passed to the VCO 140 and used to control the frequency and accordingly the phase of an output clock generated by the VCO 140. The output clock of the VCO 140 is used as the feedback clock and provided to the PFD 110. The PFD 110 then detects the phase difference between the reference clock and the feedback clock. A closed-loop control system is thus established to adjust the frequency, phase, or both of the output clock of VCO 140 to track the frequency, phase, or both, of the reference clock. In steady state, the feedback clock is locked to and aligned with the reference clock; the output current signal of the CP 120 is zero or nearly zero; and the frequency of the output clock of VCO 140 will be the same as that of the reference clock.
Frequency synthesis is an important application of PLL. A frequency synthesizer works in the same manner as a general PLL shown in FIG. 1 and described above, except that a divide-by-N circuit (not shown in FIG. 1) is provided to process the output clock of the VCO 140 to generate the feedback clock, instead of directly using the output clock of the VCO 140 as the feedback clock. For every N cycles of the VCO 140 output clock, the divide-by-N circuit generates one cycle of the feedback clock. The PFD 110 then compares the phase of the feedback clock, which is the output of the divide-by-N circuit, with that of the reference clock and generate a phase difference signal represented by UP and DN. A closed-loop control system is thus established to adjust the frequency and phase of the output clock of VCO 140, and thus accordingly the frequency and phase of the feedback clock, to track the frequency and phase of the reference clock. In steady state, the feedback clock is locked to and aligned with the reference clock; the output current signal of the CP 120 is zero or nearly zero; and the frequency of the output clock of VCO 140 will be N times of that of the reference clock.
The divide-by-N circuit for frequency synthesizer may be conveniently implemented using a divide-by-N counter if N is an integer. If N is a fractional number, a straight implementation using a counter with a fixed divisor value will not work because the divisor value of a counter should be an integer. To implement a fractional N, say N=Nint+α where Nint is an integer and α is a fractional number between 0 and 1, the divisor value for the counter is dynamically shuffled. For example, we may dynamically shuffle the divisor value between Nint and (Nint+1); the effective divisor value will be N=Nint+α if the probability (steady state frequency) of having the divisor value of (Nint+1) is α and the probability (steady state frequency) of having the divisor value of Nint (1−α). In prior art circuits, a delta-sigma modulator is often used to dynamically shuffle the divisor value.
Dynamically shuffling the divisor value effectively achieves a fractional N division. However, these shuffling causes elongated UP and DN pulses, which results in elongated current pulses from the CP and consequently causes excessive phase changes to the output clock of the VCO. Prior art fractional-N synthesizers therefore suffer from excessive phase noises.
Accordingly, a circuit that effectively generates a virtual feedback clock as if generated by a fictitious fractional-N divider circuit would have utility.